The invention generally relates to the field of memories for digital electronics, and specifically to first-in, first-out (FIFO) memories having disparate write and read clock frequencies.
A FIFO can be used to transfer data from one clock domain to another. Such FIFOs are sometimes referred to as "clock crossing FIFOs." Depending upon the relative clock frequencies, prior art clock crossing FIFOs have utilized indications set by the "write" side circuitry to inform the "read" side circuitry that at least one data unit has been written and is now available for reading. One form of such a prior art indication involves a comparison of write and read addresses. With reference to FIG. 1, the write address (WR.sub.-- PTR) increments in order to write the next data unit. A comparator compares the write address (WR.sub.-- PTR), which has been incremented, to the read address (RD.sub.-- PTR), which has not incremented. The inverted output of the comparator will therefore be set to logic one. This state can then be utilized by the read circuitry as an indicator that at least one data unit is now available for reading.
For prior art systems employing such a comparison between write pointer address and read pointer address to derive an indication of whether a data unit is ready to be read, the write pointer may be conveyed across the clock boundary using a double synchronized flip-flop circuit, such as that illustrated in FIG. 1. In this example, the write side circuitry is running at a clock rate of 25 MHz, while the read circuitry is running at 33 MHz. Four flip flops ("FF1A", "FF1B", "FF2A", "FF2B" in FIG. 1) are required, two for each bit in the two-bit WR.sub.-- PTR. The reason for using two flip flops for each bit is that a first flip flop may enter a "metastable" state when an input, arriving according to a first clock rate, is clocked into the flip flop running at a second clock rate.
With reference to FIGS. 2A and 2B, the metastable state results when a change in state at the input ("D") of a flip flop occurs within less than a specified set-up time (T.sub.SU), or a change in state at the input occurs within less than a specified hold time (T.sub.H). These times are specified by the flip flop manufacturer. The timing diagrams in these figures apply to either FF1A and FF2A, or FF1B and FF2B. The first flip flops ("FF1A" or "FF1B") are used to establish either a high or low state at the respective output ("Q") on a first clock cycle following a change in state at the input. Because of the possibility of metastability, this output is not reliable on the first clock cycle; in FIG. 2B, the output of the first flip flop settled in a logic "low" state even though the input is in a logic "high" state. The second flip flop will latch either a low or high state, but eliminates the possibility that a metastable state will be observed by the circuitry on the read side.
In FIG. 2A, the second flip flop latches the change in the WR.sub.-- PTR value on the second rising clock edge following assertion of WR.sub.-- PTR, resulting in a change in the comparator. However, in FIG. 2B, the second flip flop latches the change in WR.sub.-- PTR on the third clock cycle. This potential for delay must be accounted for in the read circuitry.
A further problem exists if the normal progression of binary numbers is utilized for the WR.sub.-- PTR. The write pointer values would normally progress in the following order: 00, 01, 10, 11. However, this progression has two instances where both bits are changing, between 01 and 10, and between 11 and 00. If it is possible that both bits might change value, it will be impossible to tell for sure if a change in WR.sub.-- PTR was the result of multiple writes, or due to metastability.
One way to address this problem is to employ a Gray Code sequence, such as: 00, 01, 11, 10. Here, only one bit changes at a time, so it is possible to determine if one of the flip flops has become metastable. However, this approach only works if the write side clock frequency is less than the read side clock frequency. Otherwise, if the write side clock frequency were, for instance, at least twice as fast as the read side clock frequency, it would be possible for the write address to change twice, thus defeating the ability to determine if one of the flip flops has become metastable since the write address may increment more than once before the read side circuitry can check it.
To address this problem, the prior art has doubled the necessary FIFO memory width, and divided down the write side clock frequency by two. Depending upon the relative clock frequencies, additional buffering and clock division may be required.
Illustrated in FIG. 3 is a further prior art configuration used by a write side circuit for signalling a read side circuit that at least one data unit is available for reading in an associated memory. Here, a first flip flop, labelled "FF1" receives a toggle signal, "T", reflecting that a data unit has been written to the memory and is now available for reading. FF1 is clocked at the write side clock rate, or 25 MHZ in the illustrated example. When latched by FF1, the Q output of FF1 goes to a high state, and the Q-inverted output goes low. This Q-inverted output is looped back to the input to reset FF1 on the next clock cycle.
The Q output of FF1 is latched on the next clock cycle of the read clock, here running at 33 MHZ. As described above, this may result in a metastable state for FF2, depending upon when the output of FF1 occurs relative to the rising edge of the read side clock. For this reason, FF3 is employed to isolate the read side circuitry from the metastable condition, as previously described.
One of the benefits of this circuit is that it accommodates the transfer of the toggle signal across the clock boundary, as opposed to transferring the entire write address. It also avoids the need to provide write-read address comparison circuitry, instead relying upon the assertion of a single toggle bit.
The drawbacks of this circuit are much the same as the circuit of FIG. 1, however. Specifically, the circuit of FIG. 3 only works in the case where the write side clock frequency is less than the read side clock frequency. Otherwise, the toggle may be reset before FF2 has latched it at the read side clock frequency.
All of the foregoing configurations must be customized according to the particular clock frequencies expected on either side of the FIFO. The prior art has thus failed to provide a clock-crossing FIFO and associated circuitry which accommodates data writes and reads regardless of clock frequencies on the respective sides.